Altera Quartus Bundle

Intel® Quartus® Prime Design Software Overview

The new revolutionary Intel® Quartus® Prime design software includes everything you need to design for Intel FPGAs, SoCs, and CPLDs from design entry and synthesis to optimization, verification, and simulation. Dramatically increased capabilities on devices with multi-million logic elements are providing designers with the ideal platform to meet next-generation design opportunities. For designers to effectively take advantage of these devices, software must dramatically increase design productivity. The new Quartus Prime software, built on the successful Quartus II software, is breaking barriers of FPGA design productivity.

The Quartus Prime software is available in three editions based on your design requirements: Pro, Standard, and Lite Edition.

• Quartus Prime Pro Edition–The Quartus Prime Pro Edition software is optimized to support the advanced features in next-generation FPGAs and SoCs, starting with the Intel Arria® 10 device family.

• Quartus Prime Standard Edition–The Quartus Prime Standard Edition software includes the most extensive support for earlier device families and requires a subscription license.

• Quartus Prime Lite Edition–The Quartus Prime Lite Edition software provides an ideal entry point to high-volume device families and is available as a free download with no license file required.

Maximizing Productivity with Devices, Tools and IP

Intel is committed to delivering a complete IP portfolio, system-level design tools, and a third-party OS ecosystem that maximizes designer productivity for industrial applications.

• Qsys is our system-level IP integration tool. Qsys is a scriptable system integration tool with a graphical front end that helps you integrate off-the-shelf and custom IP with soft and hard-core processors.
• We have had a long-term partnership with The MathWorks, and offer highly optimized HDL generation flows in the Simulink environment using our DSP Builder blockset. Additionally, we are investing heavily in high-level design tools–providing proven leadership with OpenCL for FPGAs.
• Finally, our partnership with ARM allows us to offer the state-of-the-art DS-5 tool, which offers unparalleled productivity and performance for embedded system design and debug.

Intel® Quartus® Prime Software Productivity Tools and Features

Intel® Quartus® Prime software provides everything you need to design with Intel FPGAs, SoCs, and CPLDs. It is a complete development package that comes with a user-friendly GUI and best-in-class technology to help you bring your ideas into reality. Learn more about the new and exciting features available in the Quartus Prime software

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DESIGN FLOW METHODOLOGY	BluePrint Platform	Designer Platform designer tool that enables you to quickly create your I/O design using real time legality checks.
	Pin planner	Eases the process of assigning and managing pin assignments for high-density and high-pin-count designs.
	Qsys or Qsys Pro	Automates system development by integrating IP functions and subsystems (collection of IP functions) using a hierarchical approach and a high-performance interconnect based on a network-on-a-chip architecture.
	Off-the-shelf IP cores	Let’s you construct your system-level design using IP cores from Intel and from Intel’s third-party IP partners.
	Synthesis	Now with expanded language support for System Verilog and VHDL 2008.
	Scripting support	Supports command-line operation and Tcl scripting, as well as graphical user interface (GUI) design.
	Rapid Recompile	Maximizes your productivity by reducing your compilation time up to 4X (for a small design change after a full compile). Improves design timing preservation.
	Incremental Optimization	The incremental optimizations capability in the Quartus Prime Pro Edition software offers a faster methodology to converge to design sign-off. The traditional fitter stage is divided into finer stages for more control over the design flow.
	Partial Reconfiguration	Create a physical region on the FPGA that can be reconfigured to execute different functions. Synthesize, place, route, close timing, and generate configuration bit streams for the functions implemented in the region.
PERFORMANCE AND TIMING CLOSURE METHODOLOGY	Physical synthesis	Uses post placement and routing delay knowledge of a design to improve performance.
	Design space explorer (DSE)	Increases performance by automatically iterating through combinations of Quartus Prime software settings to find optimal results.
	Extensive cross-probing	Provides support for cross-probing between verification tools and design source files.
	Optimization advisors	Provides design-specific advice to improve performance, resource usage, and power consumption.
	Chip planner	Reduces verification time while maintaining timing closure by enabling small, post placement and routing design changes to be implemented in minutes.
VERIFICATION	TimeQuest timing analyzer	Provides native Synopsys* Design Constraint (SDC) support and allows you to create, manage, and analyse complex timing constraints and quickly perform advanced timing verification.
	SignalTap II logic analyzer1	Supports the most channels, fastest clock speeds, largest sample depths, and most advanced triggering capabilities available in an embedded logic analyzer.
	System Console	Enables you to easily debug your FPGA in real time using read and write transactions. It also enables you to quickly create a GUI to help monitor and send data into your FPGA.
	PowerPlay technology	Enables you to analyze and optimize both dynamic and static power consumption accurately.