Mentor Graphics HEP1 for FPGA Design Flow (Frontend Design)

Design, Verification and Test—A solution for HDL design verification, synthesis and test of ASICs and FPGAs including: FormalPro, Vista/Vista Elite, ReqTracer, ModelSim, Precision FPGA Synthesis, LeonardoSpectrum.

HEP’s Design, Verification and Test bundle provides complete solutions for HDL design, verification, synthesis and test of ASICs and FPGAs:

  • HDL Designer – High level Design comprehensive suite of tools for design creation in HDL, graphical and analysis using C and System C.
  • Questa Advanced Functional Verification Platform – Completely standards based, Questa is the most advanced functional verification product in the industry, supporting assertion based verification, coverage driven verification, test bench automation and formal analysis of clock domain crossing, supported by a comprehensive suite of Verification IP.

  • Physical RTL synthesis for advanced-node designs with Precision-RTL.

  • FPGA Design and Verification – A complete solution comprising HDL design, simulation, hardware/software co-verification and leading FPGA logic and physical synthesis.

A complete environment for creation and verification of mixed-signal and Multilanguage systems, prevalent in automotive electrical systems, control systems and mechatronic systems.