Verilog Course

Verilog Design Course

Eligibility : BE/BTech in EEE/ECE/TE/CSE/IT/EIE/ ME/MTech/MS in Electronics/MSc Electronics

Program 1
Category : Full Time course
Duration : Two Months

Verilog Course:

Course Highlights:

• Full understanding of HDL code.
• Implementation of HDL code on FPGA.
• Avoid the common mistakes people make when they are first using Verilog
• modelling combinational and sequential hardware blocks
• Direct and Random test-benches to verify your RTL code
• Synthesizable RTL design descriptions


VLSI Course:



CHAPTER 1: Introduction
CHAPTER 2: Lexical Tokens
White Space, Comments, Numbers, Identifiers, Operators, Verilog Keywords
CHAPTER 3: Gate-Level Modeling
Basic Gates, buf, not Gates, Three-State Gates; bufif1, bufif0, notif1, notif0
CHAPTER 4: Data Types
Value Set, Wire, Reg, Input, Output, Inout, Integer, Supply0, Supply1, Time, Parameter
CHAPTER 5: Operators
Arithmetic Operators, Relational Operators, Bitwise Operators, Logical Operators, Reduction, Operators, Shift Operators, Concatenation Operator, Conditional Operator: “?” Operator Precedence
CHAPTER 6: Operands
Literals, Wires, Regs, and Parameters, Bit-Selects “x[3]” and Part-Selects “x[5:3]” Function Calls
CHAPTER 7: Modules
Module Declaration, Continuous Assignment, Module Instantiations, Parameterized Modules
CHAPTER 8: Behavioral Modeling
Procedural Assignments, Delay in Assignment, Blocking and Nonblocking Assignments begin … end, for Loops, while Loops, forever Loops, repeat, disable, if … elseif … else case, casex, casez

CHAPTER 9: Timing Controls
Delay Control, Event Control, @, Wait Statement, Intra-Assignment Delay
CHAPTER 10: Procedures: Always and Initial Blocks, Always Block, Initial Block
CHAPTER 11: Functions
Function Declaration, Function Return Value,
Function Call, Function Rules, Example
CHAPTER 12: Tasks
CHAPTER 13: Component Inference
Registers, Flip-flops, Counters, Multiplexers, Adders/Subtracters, Tri-State Buffers, Other Component Inferences
CHAPTER 14: Finite State Machines
Counters, Shift Registers
CHAPTER 15: Compiler Directives
Time Scale, Macro Definitions, Include Directive
CHAPTER 16: System Tasks and Functions
$display, $strobe, $monitor $time, $stime, $realtime, $reset, $stop, $finish $deposit, $scope, $showscope, $list
CHAPTER 17: Test Benches
Synchronous Test Bench
CHAPTER 18: Memories
Two-dimensional arrays, Initializing memory from a file.
CHAPTER 19: Verilog Reference Books
CHAPTER 20: Verilog HDL Quick Reference Card