VLSI FPGA Design Course

VLSI FPGA Design Course

This course trains you on the advanced Design and Verification technologies and methodologies. One can easily enter into the VLSI industry with the skill sets that are gained through this training course.

Key Features

  • FPGA design methodologies
  • Training and Internship
  • Advanced Logic Design
  • FPGA Architecture
  • HVL : SystemVerilog
  • HDL : Verilog
  • Assertion Based Verification: SVA
  • Two Major Projects/ One Dissertation work
  • Operating System – Linux

Introduction to VLSI FPGA Digital Design Engineering


-Revision of Basic Digital systems.

  • Combinational Circuits.
  • Sequential Circuits, Timing.
  • Electrical Characteristics.
  • Power Dissipation.

-Current state of the field.

  • SoC, IP Design, SoPC.
  • Design methodology, System Modeling, HardwareSoftware Co-design.

-Digital system Design.

  • Top down Approach to Design, Case study.
  • Data Path, Control Path.
  • Controller behavior and Design.
  • Case study Mealy & Moore Machines.
  • Timing of sequential circuits.

-Field Programmable Gate Array

-Intro to FPGAs

  • FPGA Overview
  • FPGAs vs ASIC


  • How is an FPGA Programmed?
  • What Hardware can be Implemented with an FPGA?

-FPGA Architecture

  • Basic Components of FPGA (LUT, CLB, Switch Matrix, IOB)
  • FPGA Architecture

–The FPGA Development Process

  • The FPGA Development Process
  • The Steps you Need to Take
  • Create a Project
  • Write your Code
  • Assign Pins
  • Pin Assignment Demo
  • Specify Timing Constraints
  • Propagation Delays Example
  • Timing in Sequential Systems
  • Where the Compiler Takes On
  • Timing Analysis
  • Programming Files

–Introduction to Digital design

  • Introduction to the Course
  • Introduction to VHDL

–VHDL Data Types

  • Data Types Introduction
  • Signals / Variables / Constants
  • Unsigned / Signed Data Types
  • Standard Logic Vector / Standard Logic
  • Integer / Boolean Data Types
  • Initializing Values in VHDL
  • Data Type Examples in VHDL Designs Part 1
  • Data Type Examples in VHDL Designs Part 2

–VHDL Syntax

  • VHDL Syntax Introduction
  • If Statement / Case Statement
  • For Loop / While Loop
  • VHDL For Loop Example
  • When Else Statement With Select When Statement
  • VHDL Processes and Concurrent Statement
  • VHDL Syntax Design Example
  • 1 VHDL Basics

–VHDL Coding Structure

  • Organizing Your VHDL Designs
  • VHDL Design Structure
  • VHDL Design Architecture Styles
  • Data Flow Architecture Example – Full Adder
  • Behavioral Architecture Example – Full Adder
  • Concept of VHDL Modeling
  • VHDL Coding Structure

–Test Bench

  • Test Benches Introduction
  • Test Bench Structure Walkthrough
  • Walkthrough of a Completed Test Bench
  • VHDL Test Benches

–Implementing State Machines in VHDL

  • State Machine Introduction
  • Designing a State Machine

–FPGA Development Boards

  • Supported FPGA Development Boards

–Xilinx Tools

  • Xilinx Tools Introduction
  • VHDL Simulation Tool

-Overview of VLSI Design

  • Introduction to Xilinx Vivado , RTL design using HDL
  • Functional Verification
  • Synthesis, Design Implementation
  • Xilinx Design  Constraints,  HDL Coding, Simulation and Test bench
  • Power Analysis using Vivado
  • Generate bit-stream
  • verify in Hardware

-Examples on FPGA Board 

-Xilinx VIVADO SDK design flow

  • Hardware design, Bourd Supporting Packages, C language coding
  • SDK workflow with an example
  • Generation of VIVADO IP Cores

– Targeting on FPGA